Very-large-scale integration is the art of designing chips with billions of transistors, describing hardware in code, verifying it exhaustively. Trusting foundries to manufacture it. It is electronics design at the scale where methodology is everything.
At a glance: 8 minute guide · part of the PCB design complete guide track · worked example, quick-reference table and field notes included.
The design flow
Specification becomes register-transfer-level (RTL) code in Verilog or VHDL, describing registers and the logic between them. Synthesis maps it to standard cells from the foundry's library. Place-and-route physically arranges them; static timing analysis proves the clock closes. Verification consumes most of the schedule, simulators and formal tools hunt states the silicon must never enter.
Standard cells and abstraction
Chip design survives on abstraction layers: transistors form logic gates. Gates form standard cells (inverters, flip-flops) with pre-characterised timing. Cells form blocks; blocks form the chip. Each layer trusts the one below so designers can think in systems rather than atoms.
Manufacturing and what it costs
Designs ship as GDSII files to foundries running cutting-edge nodes, 5 nm and below for phones, mature 28-180 nm for most products. Mask sets at advanced nodes cost millions. Is why ASICs demand volume and why FPGA prototyping exists to de-risk them first.
| Stage | Purpose | Tool class |
|---|---|---|
| RTL design | Describe behaviour | HDL languages |
| Verification | Prove correctness | Simulation, formal |
| Synthesis | Map to library cells | EDA synthesis |
| Place & route | Physical layout | EDA P&R |
| Sign-off | Timing, DRC, power | Analysis tools |
How to apply this in your build
Work through the sequence below. Each step assumes the previous one passed. The numbers that need arithmetic are covered by the linked tools at the end of this guide.
- Write RTL with the verification plan beside it
- Simulate at block level before integration
- Prototype riskier designs on FPGAs first
- Budget sign-off time as generously as design time
Worked example
A simple UART block: 200 lines of Verilog, a week of testbenches. It becomes one drop-in IP reused across products, abstraction is what makes billion-transistor chips humanly possible. Cross-check with the related calculator and the result should agree to within rounding.
Practical note from the bench. The VLSI lesson worth keeping even if you never tape out: verify like silicon is permanent, because it is.
Who this guide is for
First-time readers get a single focused topic instead of a textbook chapter, with every term defined where it first appears. Returning readers use it as a reference. The table, the worked example and the mistake list answer the questions that come up mid-build. If you teach, the structure (theory, application, example, failure modes) maps cleanly onto a lab session.
Prerequisites and preparation
Before starting: write rtl with the verification plan beside it and simulate at block level before integration. Keep a notebook to hand, every number in the worked example is reproducible. Total time including the bench steps: about 6 to 8 minutes.
Common mistakes to avoid
Each of these has cost real hardware on someone's bench, usually ours:
- Treating verification as an afterthought, silicon respins cost months and fortunes
- Ignoring clock domain crossings until metastability appears in the field
- Underestimating power intent at RTL, then fighting it in layout
Key takeaways
- The design flow, the foundation of this guide; revisit it if any measurement here surprises you.
- Standard cells and abstraction, the foundation of this guide; revisit it if any measurement here surprises you.
- Manufacturing and what it costs, the foundation of this guide. Revisit it if any measurement here surprises you.
Quick reference card
| Aspect | Where to find it in this guide |
|---|---|
| Core theory | The design flow |
| Application steps | How to apply this in your build |
| Worked numbers | Worked example |
| Failure modes | Common mistakes to avoid |
How this fits the PCB design complete guide track
This guide is one stop in a structured path. Start from the PCB design complete guide complete guide for the full map, or continue with board-level design and fabrication basics.
Frequently asked questions
How do I start learning VLSI? Digital logic first, then Verilog and a free simulator. FPGA boards give real feedback before any foundry is involved.
VLSI versus PCB design careers? Complementary domains: PCB engineers integrate physical systems. VLSI engineers live inside chips, many products need both, side by side.
Where do I go next? Back to the PCB design complete guide complete guide, which indexes every guide in this track and updates as new ones publish.
Continue this track
- Building a foundation? The pcb design complete guide maps every step in order.
- Next: Ground Planes and Return Paths: Signal Integrity Foundations
- Next: RF PCB Layout: Rules for WiFi, LoRa and Beyond
- Next: PCB Footprints: Pads, Courtyards and the Checks That Matter
- Work the numbers: trace width calculator · resistor decoder · SMD code decoder
Verification routine
Component substitution is a legitimate experiment as long as it is deliberate. Swap one part, predict the effect, measure, and record. That single habit converts a parts bin into a teaching lab and makes every future guide in this track faster to absorb.
The fastest way to internalise this topic is to change one variable deliberately and predict the result before measuring. Wrong predictions are the curriculum, they show exactly which mental model needs revisiting, and the bench grades honestly.
Formulas and checks from this guide
Verification checklist for this track: run DRC early and often, verify footprints against the datasheet drawing. Walk the return path of every fast signal before ordering. A five-minute Gerber preview has saved more fab cycles than any other habit.
Bookmark this page against your next build in the track. The checklist above is the same one used across 15 guides in this series.
Notes from the bench
Two for hobby density, four the moment ground integrity or impedance matters. The cost gap has collapsed.
Run DRC continuously, then once more after every final edit. The last small change breaks the most boards.
Before you close this tab
A note on layout order, which decides most boards in this track: connectors, then ICs with decoupling, then critical routes, then fill. Reversing that order is how revisions multiply.
Working through The design flowand Standard cells and abstraction with that habit in mind takes minutes, and it is the difference between reading about this topic and owning it.
Extended Application Notes
This section expands the practical application of what is vlsi design? building chips with billions of transistors beyond the worked example, into the situations builders actually meet. Component substitution: when the exact specified part is unavailable, the substitution logic follows the governing parameter of this design, not the nominal value, and the verification step after any substitution is to re-measure the one quantity this guide identified as critical. Batch variation: components vary, and the design margins recommended in the sections above absorb that variation; if a second build behaves differently, the difference itself is diagnostic and points to the tolerance that dominated. Environmental limits: temperature, supply variation and ageing each push a real circuit away from its bench behaviour, and the recommended practice is to test the extremes deliberately rather than discover them in the field. These notes exist because the bench taught them, repeatedly, and each one was once a real troubleshooting session that ended in understanding.
Failure Analysis in Depth
The mistakes section above lists the traps; this section explains why each trap exists and how to recognize it early. Treating verification as an afterthought, silicon respins cost months and fortunes Ignoring clock domain crossings until metastability appears in the field Underestimating power intent at RTL, then fighting it in layout. Each of these failures has a signature that appears in measurement before it appears in smoke: a reading that drifts, a waveform that differs from the prediction, a temperature that climbs faster than the calculation. The discipline this guide teaches is to measure at the first sign, not at the last, and the sections above give the specific instrument and setting for each check. Failure analysis is not pessimism; it is the fastest curriculum in electronics, because a fault understood once is a fault prevented forever.
Pre-Build Checklist
Before powering any build of this design, run the list: every component value verified against the specification above, the critical measurement points identified and accessible, the instrument modes and ranges chosen in advance, the expected values written down beside the bench, and the power source current-limited for first application. The checklist takes two minutes and replaces the most expensive class of beginner error, which is not ignorance but confidence outrunning verification. Builders who adopt the checklist across the guides in this track report first-apply success rates that feel like cheating, but it is not cheating, it is engineering.
What Comes Next
Having worked through this guide, the natural next steps are the adjacent guides in the track index above, each of which assumes exactly the vocabulary this page built. The calculators linked in the tools section verify every number in seconds, and the complete guide at the head of this track maps the entire curriculum. Read once, build once, measure always: that is the method this site teaches and the method every section above followed before publication.
Theory in Practice, Extended
The theory section of what is vlsi design? building chips with billions of transistors deserves one more pass with the bench in mind, because knowing a relationship and applying it under constraint are different skills. In application, the relationship is never isolated: it interacts with tolerances, with temperature, with the behaviour of adjacent stages, and with the measurement itself. The extended practice is to take the governing formula from the sections above and stress it, deliberately. Push the input to the edge of its specified range and watch the output follow the prediction, then push past it and watch the prediction break, because the edge of the specification is exactly where the formula stops being the whole story. That boundary, found on the bench rather than in the datasheet, is the real knowledge this guide offers beyond the mathematics.
Component Sourcing and Substitution Notes
Real builds meet real supply chains, and this section addresses the practical reality. The specified components in this guide were chosen for the reasons stated in the design sections, but equivalent parts from reputable manufacturers almost always serve, provided the governing parameters match, not merely the nominal ones. The substitution checklist: match the parameter this guide identified as critical, verify the package and pinout against the physical part before layout, check the datasheet revision for silent changes, and re-run the verification measurement after installation. Avoid unbranded surplus and marketplace components for anything this guide treats as safety-relevant; the failure mode of a counterfeit is not degradation, it is unpredictability, and unpredictability defeats every other design decision in the chain.
Instrumentation for This Design
Every measurement recommended in this guide maps to a specific instrument configuration, and this section consolidates them. Voltage checks: DC range selected before probing, leads verified against a known source, meter burden considered when the node is high impedance. Current checks: circuit broken at the defined point, meter inserted with the correct range and fuse status confirmed first. Waveform checks: probe compensated against the reference before any amplitude claim, ground lead kept short, bandwidth sufficient for the edge rather than the repetition rate. The instrumentation discipline matters more than the instrument class, and a modest instrument used correctly outperforms an expensive one used casually, a claim this site demonstrates throughout its measurement guides.
Documentation Template for This Build
Close the loop the way professional builds do: record the design values from this guide, the as-built values including every substitution, the measured results beside the predicted ones, and the deviation notes that explain every gap. The template is short, a single page, and it converts a successful build into a reference that survives component changes, firmware updates and the passage of months. Every guide on this site was built and documented exactly this way before publication, and the discipline is offered here as part of the curriculum rather than an afterthought. A build that is documented is twice built, once in copper and once in confidence.
Last updated 23 August 2026